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STR720 Datasheet(PDF) 306 Page - STMicroelectronics

No. de pieza STR720
Descripción Electrónicos  ARM720T 16/32-BIT MCU WITH 16K RAM, USB, CAN, 3 TIMERS, ADC, 6 COMMUNICATIONS INTERFACES
PDF  401 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STR720 Datasheet(HTML) 306 Page - STMicroelectronics

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STR720 - WATCHDOG TIMER (WDG)
306/401
WDT Prescaler Register (WDTPR)
Address Offset: 04h
Reset value: 00FFh
Bit 15:8 = Reserved.
Bit 7:0 = PR[7:0]: Prescaler value.
The clock to Timer Counter is divided by PR[7:0]+1.
This value takes effect when Watchdog mode is enabled (WE bit is put to ‘1’) or the re-load
sequence occurs or the Counter starts (SC) bit is put to ‘1’ in Timer mode.
WDT pre-load Value Register (WDTVR)
Address Offset: 08h
Reset value: FFFFh
Bit 15:0 = TV[15:0]: Timer Pre-load Value
This value is loaded in the Timer Counter when it starts counting or a re-load sequence
occurs or an End of Count is reached. The time (
µs) need to reach the end of count is given
by:
(PR[7:0]+1)*(TV[15:0]+1)*TCK/1000 (µs)
where TCK is the Watchdog clock period measured in ns.
I.e. if FCK = 20MHz the default timeout set after the system reset is 256*65536*50/1000 =
838861
µs.
15
14
13
12
11
10
9
8
765432
1
0
reserved
PR7
PR6
PR5
PR4
PR3
PR2
PR1
PR0
-
rwrwrwrwrwrw
rw
rw
15
14
13
12
11
10
9
8
765432
1
0
TV15
TV14
TV13
TV12
TV11
TV10
TV9
TV8
TV7
TV6
TV5
TV4
TV3
TV2
TV1
TV0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
1



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