STR720 datasheet(353/401 Pages) STMICROELECTRONICS

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STR720 - MISCELLANEA REGISTERS (GCR - CGC - AHB_ERR)

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S-APB Global Configuration Register 2 (SGCR2)

Address: 0xF000_0C04

Reset value: 0x00XX

This register collects internal configuration signals status so that application software can

check them, if required. This is a read-only register.

Bit 15:1 = Reserved. These bits will be always read back as ‘0’.

Bit 0 = EXT_BOOT: EXTernal BOOT

This bit reports the status of P3.8 pin at RSTIN rising edge, which is used to configure the

boot mode of the device, selecting if reset vector is fetched from EMI address space. After

reset rising edge P3.8 can change its value, according to application requirements, but boot

mode cannot be changed unless a new hardware reset is applied to the device.

0: Reserved ROM mode.

1: STR720 boots from external EMI area.

S-APB Global Configuration Register 3 (SGCR3)

Address: 0xF000_0C08

Reset value: 0x0000

This register configures the DMA request assignment to the available DMA streams.

Bit 15:8 = Reserved. These bits must be always written to 0.

Bit 7:6 = ST3_SEL[1:0]: DMA STream3 SELection

This bit field selects which DMA-capable peripheral is associated to DMA Stream 3 request:

00: BSPI1 transmit DMA request

01: ADC sample ready request.

10: Reserved. This value should never be used.

11: Reserved. This value should never be used.

Bit 5:0= Reserved. These bits must be always written to 0.

765432

Reserved

EXT_

BOOT

-r

765432

Reserved

ST3_SEL

Reserved

-rw

STR720 Datasheet(PDF) 353 Page - STMicroelectronics