STR720 datasheet(381/401 Pages) STMICROELECTRONICS

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STR720 - ELECTRICAL CHARACTERISTICS

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28.7.2

CLK pad characteristics (External Clock Source)

These pads are used to provide clock signal to STR720 system from an external clock source.

Since their electrical characteristics are different from normal I/O pads they are hereafter

reported in a specific table.

VDD(all) = 1.80 V ± 10%, VDD3(all) = 3.30 V ± 10%, TA = -40 / +85 °C unless otherwise specified.

Data based on design guidelines and validation, not tested in production.

Table 94. DC CLK pad characteristics

Symbol

Parameter

Test Conditions(1)

Value

Unit

Min

Typ

Max

VDD3P

Supply Voltage for CLK input

buffer.

3.14

3.30

3.47

VREF

Reference Voltage for CLK

input signal (2)

VREF =(VDD3P -1)*0.9

± 60 mV

1.87

2.1

2.28

VREF_R

Recommended reference Volt-

age for CLK input signal

1.6

2.0

VIHP

(CLK)

Main CLK Clock (CLK) Input

high level (2)

See Figure 75

VREF + 0.2

VILP

(CLK)

Main CLK Clock (CLK) Input

low level (2)

See Figure 75

VREF - 0.2

Table 95. AC CLK pad characteristics

Symbol

Parameter

Conditions

Value

Unit

Min

Typ

Max

tw(HP)

tw(LP)

Main CLK Clock (CLK) high or

low time (2)

See Figure 75

14.29

tr(P)

tf(P)

Main CLK Clock (CLK) rise or

fall time (2)

See Figure 75

CLK Input leakage current

VSS ≤ VIN ≤ VDD3P

±1

µA

IDD3P_R

VDD3P RUN/IDLE mode cur-

rent

-2.75-

IDD3P_S

VDD3P SLOW/STOP mode

current

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