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STM32WLE4JC Datasheet(PDF) 116 Page - STMicroelectronics |
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STM32WLE4JC Datasheet(HTML) 116 Page - STMicroelectronics |
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116 / 145 page ![]() Electrical characteristics STM32WLE5/E4xx 116/145 DS13105 Rev 8 10 bits 1.5(3) 43 68 3.5 100 820 7.5 214 3300 12.5 357 5600 19.5 557 10000 39.5 1129 22000 79.5 2271 39000 160.5 4586 50000 8 bits 1.5(3) 43 82 3.5 100 1500 7.5 214 3900 12.5 357 6800 19.5 557 12000 39.5 1129 27000 79.5 2271 50000 160.5 4586 50000 6 bits 1.5(3) 43 390 3.5 100 2200 7.5 214 5600 12.5 357 10000 19.5 557 15000 39.5 1129 33000 79.5 2271 50000 160.5 4586 50000 1. Guaranteed by design. 2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and disabled when VDDA ≥ 2.4 V. 3. Only allowed with VDDA > 2 V Table 78. Maximum ADC RAIN values (continued) Resolution Sampling cycle at 35 MHz (ns) Sampling time at 35 MHz (ns) Max. RAIN(1)(2)(Ω) Table 79. ADC accuracy(1)(2)(3) Symbol Parameter Conditions(4) Min Typ Max Unit ET Total unadjusted error VDDA = VREF+ = 3 V, fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C - 3 4 LSB 2 V < VDDA, VREF+ < 3.6 V, fADC = 35 MHz; fs ≤ 2.5 Msps, TA = entire range -3 6.5 1.62 V < VDDA = VREF+ < 3.6 V, TA = entire range Range 1: fADC = 35 MHz, fs ≤ 2.2 Msps Range 2: fADC = 16 MHz, fs ≤ 1.1 Msps -3 7.5 |
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