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AD9546/PCBZ Datasheet(PDF) 108 Page - Analog Devices

No. de pieza AD9546/PCBZ
Descripción Electrónicos  Dual DPLL Digitized Clock Synchronizer
PDF  205 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD9546/PCBZ Datasheet(HTML) 108 Page - Analog Devices

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AD9546
Data Sheet
Rev. 0 | Page 108 of 205
TIME
NOMINAL
(50%)
NOMINAL
(50%)
–Δt
+Δt
MODULATION EVENT
DC = 50%
50%
FIRST
MODULATION
CYCLE
SECOND
MODULATION
CYCLE
Figure 76. Balanced Modulation Waveform
NOMINAL
(50%)
NOMINAL
(50%)
TIME
–Δt
DC < 50%
50%
SECOND PULSE
UNALTERED
MODULATION EVENT
FIRST
MODULATION
CYCLE
SECOND
MODULATION
CYCLE
Figure 77. Unbalanced Modulation Waveform
DC > 50%
BALANCED
MODULATION
UNBALANCED
MODULATION
MODULATION EVENT
DC = 50%
50%
FIRST
MODULATION
CYCLE
SECOND
MODULATION
CYCLE
TIME
NOMINAL
(50%)
NOMINAL
(50%)
50%
+Δt
SECOND PULSE
UNALTERED
+Δt
–Δt
Figure 78. Alternate Modulation Polarity



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