SPC58EEX datasheet(111/154 Pages) STMICROELECTRONICS

111 / 154 page

DS11646 Rev 4

111/154

SPC58EEx, SPC58NEx

Electrical characteristics

128

3.18.2.1.4 DSPI master mode – output only

Note:

In the following table:

•

All DSPI timing specifications apply to pins when using LVDS pads for SCK and SOUT

and CMOS pad for PCS with pad driver strength as defined. Timing may degrade for weaker

output drivers.

•

TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.

Note:

In the following table:

•

All output timing is worst case and includes the mismatching of rise and fall times of the

output pads.

•

TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.

Table 58. DSPI LVDS master timing – output only – timed serial bus mode

TSB = 1 or ITSB = 1, CPOL = 0 or 1, continuous SCK clock

Symbol

Characteristic

Condition

Value

Unit

Pad drive

Load

Min

Max

1tSCK CC D SCK cycle time

LVDS

15 pF

to 50 pF

differential(1)

25.0

—

2tCSV CC D

PCS valid after

SCK(2)

(SCK with 50 pF

differential load cap.)

Very strong

25 pF

—

6.0

Strong

50 pF

—

10.5

3tCSH CC D

PCS hold after

SCK(2)

(SCK with 50 pF

differential load cap.)

Very strong

0 pF

–4.0

—

Strong

0 pF

–4.0

—

4tSDC CC D

SCK duty cycle

(SCK with 50 pF

differential load cap.)

LVDS

15 pF

to 50 pF

differential

1/2tSCK –2

1/2tSCK +2

SOUT data valid time (after SCK edge)

5tSUO CC D

SOUT data valid

time from SCK(3)

SOUT and SCK drive strength

LVDS

15 pF

to 50 pF

differential

—3.5

SOUT data hold time (after SCK edge)

6tHO CC D

SOUT data hold time

after SCK(3)

SOUT and SCK drive strength

LVDS

15 pF

to 50 pF

differential

–3.5

—

1. LVDS differential load considered is the capacitance on each terminal of the differential pair, as shown in Figure 12.

2. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This

timing value is due to pad delays and signal propagation delays.

3. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same

value.

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