STM32W108CB datasheet(198/278 Pages) STMICROELECTRONICS

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General-purpose timers

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

Bits [11:8] ETF[3:0]: External Trigger Filter

This defines the frequency used to sample the ETRP signal, fSampling, and the length of the

digital filter applied to ETRP. The digital filter is made of an event counter in which N events

are needed to validate a transition on the output:

0000: fSampling = PCLK, no filtering

0001: fSampling = PCLK, N=2

0010: fSampling = PCLK, N=4

0011: fSampling = PCLK, N=8

0100: fSampling = PCLK/2, N=

0101: fSampling = PCLK/2, N=8

0110: fSampling = PCLK/4, N=6

0111: fSampling = PCLK/4, N=8

1111: fSampling = PCLK/32, N=8

1110: fSampling = PCLK/32, N=6

1101: fSampling = PCLK/32, N=5

1100: fSampling = PCLK/16, N=8

1011: fSampling = PCLK/16, N=6

1010: fSampling = PCLK/16, N=5

1001: fSampling = PCLK/8, N=8

1000: fSampling = PCLK/8, N=6

Note: PCLK is 12 MHz when the STM32W108 is using the 24 MHz HSE OSC, and 6 MHz if

using the 12 MHz HSI RC oscillator.

Bit 7 MSM: Master/Slave Mode

0: No action

1: The effect of an event on the trigger input (TRGI) is delayed to allow exact synchronization

between the current timer and the slave (through TRGO). It is useful for synchronizing timers

on a single external event.

Bits [6:4] TS[2:0]: Trigger Selection

This bit field selects the trigger input used to synchronize the counter.

000 : Internal Trigger 0 (ITR0)

100 : TI1 Edge Detector (TI1F_ED)

101 : Filtered Timer Input 1 (TI1FP1)

110 : Filtered Timer Input 2 (TI2FP2)

111 : External Trigger input (ETRF)

Note: These bits must be changed only when they are not used (when SMS=000) to avoid

detecting spurious edges during the transition.

Bit 3 Reserved, must be kept at reset value

STM32W108CB Datasheet(PDF) 198 Page - STMicroelectronics