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STM32W108CB Datasheet(PDF) 205 Page - STMicroelectronics

No. de pieza STM32W108CB
Descripción Electrónicos  High-performance, IEEE 802.15.4 wireless system-on-chip with up to 256 Kbytes of embedded Flash memory
PDF  278 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32W108CB Datasheet(HTML) 205 Page - STMicroelectronics

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
General-purpose timers
Doc ID 16252 Rev 14
205/278
10.3.9
Timer x capture/compare mode register 2 (TIMx_CCMR2)
Address offset: 0xE01C (TIM1) and 0xF01C (TIM2)
Reset value:
0x0000 0000
The timer channels can be programmed as inputs (capture mode) or outputs (compare
mode). The direction of a channel “y” is defined by configuring the corresponding CCyS bits
in this register. All other bits have different functions in input and in output mode. For a given
bit:
●
OCxy describes its function when the channel is configured as an output (CCyS = 0)
●
ICxy describes its function when the channel is configured as an input (CCyS > 0)
In short, the same bit can have a different meaning for the input stage and for the output
stage. Care should be taken.
Output compare mode
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
OC4M[2:0]
OC4PE
OC4FE
CC4S[1:0]
Reserved
OC3M[2:0]
OC3PE
OC3FE
CC3S[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits [31:15] Reserved, must be kept at reset value
Bits [14:12] OC4M[2:0]: Output Compare 4 Mode
Define the behavior of the output reference signal OC4REF from which OC4 derives.
OC4REF is active high whereas OC4’s active level depends on the CC4P bit.
000: Frozen - The comparison between the output compare register TIMx_CCR4 and the
counter TIMx_CNT has no effect on the outputs.
001: Set OC4REF to active on match. The OC4REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 4 (TIMx_CCR4).
010: Set OC4REF to inactive on match. OC4REF signal is forced low when the counter
TIMx_CNT matches the capture/compare register 4 (TIMx_CCR4).
011: Toggle - OC4REF toggles when TIMx_CNT = TIMx_CCR4
100: Force OC4REF inactive
101: Force OC4REF active
110: PWM mode 1 - In up-counting, OC4REF is active as long as TIMx_CNT < TIMx_CCR4,
otherwise OC4REF is inactive. In down-counting, OC4REF is inactive if
TIMx_CNT > TIMx_CCR4, otherwise OC4REF is active.
111: PWM mode 2 - In up-counting, OC4REF is inactive if TIMx_CNT < TIMx_CCR4,
otherwise OC4REF is active. In down-counting, OC4REF is active if
TIMx_CNT > TIMx_CCR4, otherwise it is inactive.
Note: In PWM mode 1 or 2, the OC4REF level changes only when the result of the
comparison changes or when the output compare mode switches from “frozen” mode to
“PWM” mode.



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