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STM32W108CB Datasheet(PDF) 210 Page - STMicroelectronics |
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STM32W108CB Datasheet(HTML) 210 Page - STMicroelectronics |
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210 / 278 page  General-purpose timers STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 210/278 Doc ID 16252 Rev 14 10.3.11 Timer x counter register (TIMx_CNT) Address offset: 0xE024 (TIM1) and 0xF024 (TIM2) Reset value: 0x0000 0000 Reserved, must be kept at reset value CNT[15:0]: Counter value 10.3.12 Timer x prescaler register (TIMx_PSC) Address offset: 0xE028 (TIM1) and 0xF028 (TIM2) Reset value: 0x0000 0000 Reserved, must be kept at reset value PSC[3:0]: Prescaler value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits [31:16] Bits [15:0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PSC[3:0] rw rw rw rw Bits [31:4] Bits [3:0] The prescaler divides the internal timer clock frequency. The counter clock frequency CK_CNT is equal to fCK_PSC / (2 ^ PSC[3:0]). Clock division factors can range from 1 through 32768. The division factor is loaded into the shadow prescaler register at each update event (including when the counter is cleared through UG bit of TIM1_EGR register or through the trigger controller when configured in reset mode). |
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