STM32H7B3II datasheet(150/238 Pages) STMICROELECTRONICS

150 / 238 page

Ideal transfer curve.

End point correlation line.

ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.

EO = Offset Error: deviation between the first actual transition and the first ideal one.

EG = Gain Error: deviation between the last ideal transition and the last actual one.

ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.

EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation

line.

Figure 56. Typical connection diagram using the ADC with FT/TT pins featuring analog switch function

MSv67871V3

Sample-and-hold ADC converter

Converter

Cparasitic(2)

Ilkg(3)

CADC

VDDA(4)

RAIN(1)

VAIN

RADC

VREF+(4)

VSSA

I/O

analog

switch

Sampling

switch with

multiplexing

VSS

Refer to Table 93. ADC characteristics for the values of RAIN and CADC.

Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (refer to Table 65. I/O static characteristics). A high Cparasitic value downgrades conversion

accuracy. To remedy this, fADC should be reduced.

Refer to Table 65. I/O static characteristics for the value of Ilkg.

Refer to .Figure 21. Power supply scheme.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 57. Power supply and reference decoupling

(VREF+ not connected to VDDA) or Figure 58. Power supply and reference decoupling (VREF+ connected to VDDA),

depending on whether VREF+ is connected to VDDA or not. The 100 nF capacitors should be ceramic (good

quality). They should be placed them as close as possible to the chip.

STM32H7B3xI

Operating conditions

DS13139 - Rev 8

page 150/238

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