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STM32H7B3II Datasheet(PDF) 159 Page - STMicroelectronics |
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STM32H7B3II Datasheet(HTML) 159 Page - STMicroelectronics |
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159 / 238 page  Symbol Parameter Conditions Min(1) Typ(1) Max(1) Unit TRIMOFFSETN, TRIMLPOFFSETN Offset trim step at high common input voltage (0.9*VDDA) mV - - 1.1 1.5 ILOAD Drive current - - - 500 μA ILOAD_PGA Drive current in PGA mode - - - 270 CLOAD Capacitive load - - - 50 pF CMRR Common mode rejection ratio - - 80 - dB PSRR Power supply rejection ratio CLOAD ≤ 50pf / RLOAD ≥ 4 kΩ(2) at 1 kHz, Vcom=VDDA/2 50 66 - dB GBW Gain bandwidth for high supply range 200 mV ≤ Output dynamic range ≤ VDDA - 200 mV 4 7.3 12.3 MHz SR Slew rate (from 10% and 90% of output voltage) Normal mode - 3 - V/µs High-speed mode - 24 - AO Open loop gain 200 mV ≤ Output dynamic range ≤ VDDA - 200 mV 59 90 129 dB φm Phase margin - - 55 - ° GM Gain margin - - 12 - dB VOHSAT High saturation voltage Iload=max or RLOAD=min, Input at VDDA VDDA −100 mV - - mV VOLSAT Low saturation voltage Iload=max or RLOAD=min, Input at 0 V - - 100 tWAKEUP Wake up time from OFF state Normal mode CLOAD ≤ 50pf, RLOAD ≥ 4 kΩ, follower configuration - 0.8 3.2 µs High speed mode CLOAD ≤ 50pf, RLOAD ≥ 4 kΩ, follower configuration - 0.9 2.8 PGA gain Non inverting gain error value PGA gain = 2 −1 - 1 % PGA gain = 4 −2 - 2 PGA gain = 8 −2.5 - 2.5 PGA gain = 16 −3 - 3 Inverting gain error value PGA gain = 2 −1 - 1 PGA gain = 4 −1 - 1 PGA gain = 8 −2 - 2 PGA gain = 16 −3 - 3 External non-inverting gain error value PGA gain = 2 −1 - 1 PGA gain = 4 −3 - 3 PGA gain = 8 −3.5 - 3.5 PGA gain = 16 −4 - 4 Rnetwork R2/R1 internal resistance values in non-inverting PGA mode(3) PGA Gain=2 - 10/10 - kΩ/ kΩ PGA Gain=4 - 30/10 - PGA Gain=8 - 70/10 - PGA Gain=16 - 150/10 - R2/R1 internal resistance values in inverting PGA mode(3) PGA Gain = -1 - 10/10 - PGA Gain = -3 - 30/10 - STM32H7B3xI Operating conditions DS13139 - Rev 8 page 159/238 |
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