ST7260 datasheet(114/117 Pages) STMICROELECTRONICS

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ST7260

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16 KNOWN LIMITATIONS

16.1 PA2 LIMITATION WITH OCMP1 ENABLED

Description

This limitation affects only Rev B Flash devices

(with Internal Sales Type 72F60xxxxx$x7); it has

been corrected in Rev W Flash devices (with Inter-

nal Sales Type 72F60xxxxx$x9).

Note: Refer to Figure 68 on page 115

When Output Compare 1 function (OCMP1) on pin

PA6 is enabled by setting the OC1E bit in the

TCR2 register, pin PA2 is also affected.

In particular, the PA2 pin is forced to be floating

even if port configuration (PADDR+PADR) has set

it as output low. However, it can be still used as an

input.

16.2 UNEXPECTED RESET FETCH

If an interrupt request occurs while a "POP CC" in-

struction is executed, the interrupt controller does

not recognise the source of the interrupt and, by

default, passes the RESET vector address to the

CPU.

Workaround

To solve this issue, a "POP CC" instruction must

always be preceded by a "SIM" instruction.

16.3 SCI WRONG BREAK DURATION

Description

A single break character is sent by setting and re-

setting the SBK bit in the SCICR2 register. In

some cases, the break character may have a long-

er duration than expected:

- 20 bits instead of 10 bits if M=0

- 22 bits instead of 11 bits if M=1.

In the same way, as long as the SBK bit is set,

break characters are sent to the TDO pin. This

may lead to generate one break more than expect-

ed.

Occurrence

The occurrence of the problem is random and pro-

portional to the baudrate. With a transmit frequen-

19200

baud

(fCPU=8MHz

and

SCI-

BRR=0xC9), the wrong break duration occurrence

is around 1%.

Workaround

If this wrong duration is not compliant with the

communication protocol in the application, soft-

ware can request that an Idle line be generated

before the break character. In this case, the break

duration is always correct assuming the applica-

tion is not doing anything between the idle and the

break. This can be ensured by temporarily disa-

bling interrupts.

The exact sequence is:

- Disable interrupts

- Reset and Set TE (IDLE request)

- Set and Reset SBK (Break Request)

- Re-enable interrupts

16.4 USB Behavior with LVD Disabled

On ROM devices, if the LVD is disabled, the USB

is disabled by hardware. So, the LVD is forced by

ST to 0 (LVD enabled). Refer to the ST7260 option

list for details.

ST7260 Datasheet(PDF) 114 Page - STMicroelectronics

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