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ES9842PRO Datasheet(PDF) 143 Page - ESS Technology,Inc

No. de pieza ES9842PRO
Descripción Electrónicos  32-bit High-Performance 4-Channel ADC
PDF  167 Pages
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Fabricante Electrónico  ESS [ESS Technology,Inc]
Página de inicio  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES9842PRO Datasheet(HTML) 143 Page - ESS Technology,Inc

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VERSION 0.5
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM
ES9842 PRO Product Datasheet
143
Synchronous Slave Interface Registers
Register 192: SOFT RESET
Bits
[7]
[6:0]
Default
1'b0
7'd0
Bits
Mnemonic
Description
[7]
AO_SOFT_RESET
Performs soft reset to digital core except for the synchronous
registers.
[6:0]
RESERVED
NA
Register 193: CLK SELECT
Bits
[7:3]
[2:1]
[0]
Default
5'd0
2'd0
1'b0
Bits
Mnemonic
Description
[7:3]
RESERVED
NA
[2:1]
SEL_SYSCLK_IN
Selects digital core and ADC clock source when EN_ANA_CLKIN is
set.
• 2'd0: XTAL (default)
• 2'd1: MCLK
• 2'd2: ACLK
• 2'd3: Reserved
[0]
EN_ANA_CLKIN
Enables clock outputs to the digital core and ADC.
• 1'b0: Disabled (default)
• 1'b1: Enabled



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