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SN65HVD230 Datasheet(PDF) 7 Page - Texas Instruments |
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SN65HVD230 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 32 page  www.ti.com RECEIVER ELECTRICAL CHARACTERISTICS RECEIVER SWITCHING CHARACTERISTICS DEVICE SWITCHING CHARACTERISTICS DEVICE CONTROL-PIN CHARACTERISTICS SN65HVD230 SN65HVD231 SN65HVD232 SLOS346H – MARCH 2001 – REVISED JULY 2006 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VIT+ Positive-going input threshold voltage 750 900 mV See Table 1 VIT- Negative-going input threshold voltage 500 650 mV Vhys Hysteresis voltage (VIT+ - VIT-) 100 VOH High-level output voltage -6 V ≤ V ID ≤ 500 mV, IO = -8 mA, See Figure 5 2.4 V VOL Low-level output voltage 900 mV ≤ V ID ≤ 6 V, IO = 8 mA, See Figure 5 0.4 VIH = 7 V 100 250 µA VIH = 7 V, VCC = 0 V 100 350 Other input at 0 V, II Bus input current D = 3 V VIH = -2 V -200 -30 µA VIH = -2 V, VCC = 0 V -100 -20 Pin-to-ground, Ci CANH, CANL input capacitance V(D) = 3 V, 32 pF VI = 0.4 sin(4E6πt) + 0.5 V Pin-to-pin, Cdiff Differential input capacitance V(D) = 3 V, 16 pF VI = 0.4 sin(4E6πt) + 0.5 V Rdiff Differential input resistance Pin-to-pin, V(D) = 3 V 40 70 100 k Ω RI CANH, CANL input resistance 20 35 50 k Ω ICC Supply current See driver (1) All typical values are at 25 °C and with a 3.3-V supply. over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low-to-high-level output 35 50 ns tPHL Propagation delay time, high-to-low-level output See Figure 6 35 50 ns tsk(p) Pulse skew (|tPHL - tPLH|) 10 ns tr Output signal rise time 1.5 ns See Figure 6 tf Output signal fall time 1.5 ns over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(Rs) = 0 V, See Figure 9 70 115 Total loop delay, driver input to receiver t(LOOP1) RS with 10 kΩ to ground, See Figure 9 105 175 ns output, recessive to dominant RS with 100 kΩ to ground, See Figure 9 535 920 V(Rs) = 0 V, See Figure 9 100 135 Total loop delay, driver input to receiver t(LOOP2) RS with 10 kΩ to ground, See Figure 9 155 185 ns output, dominant to recessive RS with 100 kΩ to ground, See Figure 9 830 990 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT SN65HVD230 wake-up time from standby mode 0.55 1.5 µs with RS t(WAKE) See Figure 8 SN65HVD231 wake-up time from sleep mode with 3 5 µs RS (1) All typical values are at 25 °C and with a 3.3-V supply. 7 Submit Documentation Feedback |
Número de pieza similar - SN65HVD230_06 |
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Descripción similar - SN65HVD230_06 |
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