HCS08 datasheet(108/290 Pages) MOTOROLA

108 / 290 page

Internal Clock Generator (ICG) Module

MC9S08GB/GT

108

MOTOROLA

6.5.5 ICG Filter Registers (ICGFLTU, ICGFLTL)

Figure 6-16 ICG Upper Filter Register (ICGFLTU)

Figure 6-17 ICG Lower Filter Register (ICGFLTL)

The filter registers show the filter value (FLT).

FLT — Filter Value

The FLT bits indicate the current filter value, which controls the DCO frequency. The FLT bits are

read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00). In

self-clocked mode, any write to ICGFLTU updates the current 12-bit filter value. Writes to the

ICGFLTU register will not affect FLT if a previous latch sequence is not complete.

6.5.6 ICG Trim Register (ICGTRM)

Figure 6-18 ICG Trim Register (ICGTRM)

TRIM — ICG Trim Setting

The TRIM bits control the internal reference generator frequency. They allow a

± 25% adjustment of

the nominal (POR) period. The bit’s effect on period is binary weighted (i.e., bit 1 will adjust twice as

much as changing bit 0). Increasing the binary value in TRIM will increase the period and decreasing

the value will decrease the period.

Bit 15

Bit 8

Read:

0000

FLT

Write:

Reset:

00000000

= Unimplemented or Reserved

Bit 7

654321

Bit 0

Read:

FLT

Write:

Reset:

11000000

76543210

Read:

TRIM

Write:

POR:

10000000

Reset:

UUUUUUUU

U = Unaffected by MCU reset

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