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STPMIC25APQR Datasheet(PDF) 115 Page - STMicroelectronics |
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STPMIC25APQR Datasheet(HTML) 115 Page - STMicroelectronics |
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115 / 145 page ![]() 6.8.7 NVM rank shadow register 5 (NVM_RANK_SHR5) Table 87. NVM_RANK_SHR5 7 6 5 4 3 2 1 0 reserved reserved LDO2_RANK[2:0] LDO1_RANK[2:0] R R R/W R/W R/W R/W R/W R/W Address: 0x96 Default: Depends on the PMIC part number Description: NVM rank shadow register 5 (see Section 5.2). [7:6] reserved [5:3] LDO2_RANK[2:0]: 000: rank0 001: rank1 010: rank2 011: rank3 100: rank4 101: rank5 110: rank0 111: rank0 [2:0] LDO1_RANK[2:0]: 000: rank0 001: rank1 010: rank2 011: rank3 100: rank4 101: rank5 110: rank0 111: rank0 STPMIC25 Register descriptions DS14278 - Rev 3 page 115/145 |
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