STM32H563VG datasheet(229/270 Pages) STMICROELECTRONICS

229 / 270 page

DS14258 Rev 5

229/270

STM32H562xx and STM32H563xx

Electrical characteristics

238

SAI characteristics

Unless otherwise specified, the parameters given in Table 121 are derived from tests

performed under the ambient temperature, fPCLKx frequency and VDD supply voltage

conditions summarized in Table 20, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

•

Capacitive load CL = 30 pF

•

I/O compensation cell activated

•

Measurement points are done at CMOS levels: 0.5 VDD

•

VOS level set to VOS0

Refer to Section 5.3.15 for more details on the input/output alternate function characteristics

(SCK, SD, WS).

RDCP_DAT

Dedicated charging port resistance

across D+/D-

200

Ω

VLGC_HI

Logic high

2.0

3.6

VLGC_LOW

Logic low

0.8

VLGC

Logic threshold

0.8

2.0

VDAT_REF

Data detect voltage

0.25

0.4

VDP_SRC

D+ source voltage

0.5

0.7

VDM_SRC

D- source voltage

0.5

0.7

IDP_SINK

D+ sink current

175

μA

IDM_SINK

D- sink current

175

1. Specified by design - Not tested in production.

Table 120. USB BCD DC electrical characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 121. SAI characteristics(1)

Symbol

Parameter

Conditions

Min

Max

Unit

fMCK

SAI main clock output

MHz

fCK

SAI clock frequency

Master transmitter, 2.7 V ≤ VDD ≤ 3.6 V

Master transmitter, 1.71 V ≤ VDD ≤ 3.6 V

Master receiver, 1.71 V ≤ VDD ≤ 3.6 V

Slave transmitter, 2.7 V ≤ VDD ≤ 3.6 V

Slave transmitter, 1.71 V ≤ VDD ≤ 3.6 V

Slave receiver, 1.71 V ≤ VDD ≤ 3.6 V

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