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STM32H563IIK6 Datasheet(PDF) 220 Page - STMicroelectronics |
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STM32H563IIK6 Datasheet(HTML) 220 Page - STMicroelectronics |
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220 / 270 page ![]() Electrical characteristics STM32H562xx and STM32H563xx 220/270 DS14258 Rev 5 Table 112. USART characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fCK USART clock frequency Master receiver 1.71 V < VDD < 3.6 V -- 31 MHz Master transmitter 1.71 V < VDD < 3.6 V 31/6(2) Master transmitter 2.7 V < VDD < 3.6 V 31/6(2) Slave receiver 1.71 V < VDD < 3.6 V 83 Slave transmitter 1.71 V < VDD < 3.6 V 32/6(2) Slave transmitter 2.7 V < VDD < 3.6 V 35/6(2) tsu(NSS) NSS setup time Slave mode tker(3) + 3.5 - - ns th(NSS) NSS hold time Slave mode 2.5 - - tw(SCKH) tw(SCKL) CK high and low time Master mode 1/fck/2 -1 1/fck/2 1/fck/2 +1 tsu(RX) Data input setup time Master mode 13 - - Slave mode 3.5 - - th(RX) Data input hold time Master mode 0.5 - - Slave mode 1.5 - - tv(TX) Data output valid time Slave mode, 1.71 V < VDD < 3.6 V - 11.5 15.5/71(2) Slave mode, 2.7 V < VDD < 3.6 V - 14/35(2) Slave mode, 1.71 V < VDD < 3.6 V - 2.5 3/52(2) Slave mode, 2.7 V < VDD < 3.6 V -3/22(2) th(TX) Data output hold time Slave mode 7.5 - - ns Master mode 0 - - 1. Evaluated by characterization - Not tested in production. 2. For PB14 with OSPEEDRy[1:0] = 01. 3. Tker is the usart_ker_ck_pres clock period. |
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