STM32MP151AAA3 datasheet(165/245 Pages) STMICROELECTRONICS

165 / 245 page

DS12500 Rev 1

165/245

STM32MP151A

Electrical characteristics

228

Output buffer timing characteristics (IO structure with _h, HSLV option

enabled)

The HSLVEN_xx bits of SYSCFG_IOCTRLSETR register (together with OTP bit

PRODUCT_BELOW_2V5) can be used to optimize the I/O speed when the product voltage

is below 2.5 V typ. (2.7 V max.).

4. Compensation system enabled.

Table 51. Output timing characteristics (HSLV ON, _h IO structure)(1)

Speed

Symbol

Parameter

conditions

Min

Max

Unit

Fmax(2)

Maximum frequency

C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V

MHz

C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V

C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V

C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V

tr/tf(3)

Output high to low level

fall time and output low

to high level rise time

C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V

9.9

C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V

8.1

C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V

7.1

C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V

5.8

Fmax(2)

Maximum frequency

C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V

MHz

C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V

C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V

C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V

100

tr/tf(3)

Output high to low level

fall time and output low

to high level rise time

C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V

5.7

C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V

4.2

C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V

3.5

C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V

2.7

Fmax(2)

Maximum frequency

C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)

-71

MHz

C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)

-101

C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)

-126

C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)

-162

tr/tf(3)

Output high to low level

fall time and output low

to high level rise time

C = 50 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)

-4.7

C = 30 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)

-3.3

C = 20 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)

-2.7

C = 10 pF, 1.71 V ≤ VDD ≤ 2.7 V(4)

-1.9

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