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STM32L4P5CE Datasheet(PDF) 241 Page - STMicroelectronics

No. de pieza STM32L4P5CE
Descripción Electrónicos  Ultra-low-power Arm® Cortex®-M4 32-bit MCUFPU, 150 DMIPS, up to 1-MB Flash memory, 320-KB SRAM, LCD-TFT, ext. SMPS
PDF  311 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L4P5CE Datasheet(HTML) 241 Page - STMicroelectronics

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DS12903 Rev 2
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STM32L4P5xx
Electrical characteristics
277
Figure 42. SPI timing diagram - slave mode and CPHA = 0
tdis(SO) Data output disable time Slave mode
9
-
16
ns
tv(SO)
Data output valid time
Slave mode 2.7 V < VDD < 3.6 V
Voltage Range V1
-
13
15.5
Slave mode 1.71 V < VDD < 3.6 V
Voltage Range V1
-11
23
Slave mode 1.71 V < VDD < 3.6 V
Voltage Range V2
-13
22
Slave mode(3)
1.08 V < VDD < 1.32 V
-27
30
tv(MO)
Master mode
-
2
4
th(SO)
Data output hold time
Slave mode 1.71 V < VDD < 3.6 V
9
-
-
Slave mode(3)
1.08 < VDD < 1.32 V
24
-
-
th(MO)
Master mode
1
-
-
1. Guaranteed by characterization results.
2. The maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into
SCK low or high-phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a
master having tsu(MI) = 0 while Duty(SCK) = 50%.
3. SPI mapped on GPIOG port which is supplied by VDDIO2 specified down to 1.08V. SPI is tested in this voltage.
Table 96. SPI characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max(2)
Unit
MSv41658V1
NSS input
CPHA=0
CPOL=0
CPHA=0
CPOL=1
MISO output
MOSI input
tsu(SI)
th(SI)
tw(SCKL)
tw(SCKH)
tc(SCK)
tr(SCK)
th(NSS)
tdis(SO)
tsu(NSS)
ta(SO)
tv(SO)
Next bits IN
Last bit OUT
First bit IN
First bit OUT
Next bits OUT
th(SO)
tf(SCK)
Last bit IN



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