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ST90135 Datasheet(PDF) 169 Page - STMicroelectronics |
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ST90135 Datasheet(HTML) 169 Page - STMicroelectronics |
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169 / 190 page ![]() 169/190 ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) ANALOG TO DIGITAL CONVERTER (Cont’d) Figure 88. Application Example: Analog Watchdog used in Motorspeed Control n 9.6.3 Interrupts The A/D provides two interrupt sources: – End of Conversion – Analog Watchdog Request The A/D Interrupt Vector Register (AD_IVR) pro- vides hardware generated flags which indicate the interrupt source, thus allowing automatic selection of the correct interrupt service routine. The A/D Interrupt vector should be programmed by the User to point to the first memory location in the Interrupt Vector table containing the base ad- dress of the four byte area of the interrupt vector table in which the address of the A/D interrupt service routines are stored. The Analog Watchdog Interrupt Pending bit (AWD, AD_ICR.6), is automatically set by hardware whenever any of the two guarded analog inputs go out of range. The Compare Result Register (CRR) tracks the analog inputs which exceed their pro- grammed thresholds. When two requests occur simultaneously, the An- alog Watchdog Request has priority over the End of Conversion request, which is held pending. The Analog Watchdog Request requires the user to poll the Compare Result Register (CRR) to de- termine which of the four thresholds has been ex- ceeded. The threshold status bits are set to flag an out of range condition, and are automatically reset by hardware after a software reset of the Analog Watchdog Request flag in the AD_ICR Register. The interrupt pending flags, ECV and AWD, should be reset by the user within the interrupt service routine. Setting either of these two bits by software will cause an interrupt request to be gen- erated. 9.6.3.1 Register Mapping It is possible to have two independent A/D convert- ers in the same device. In this case they are named A/D 0 and A/D 1. If the device has one A/D converter it uses the register addresses of A/D 0. The register pages are the following: Analog Watch- dog Re- quest 70 Lower Word Address X X XX XX 0 0 End of Conv. Request 70 Upper Word Address X X XX XX 1 0 A/Dn Register Page A/D 0 63 A/D 1 61 9 |
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