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H8SX1663 Datasheet(PDF) 783 Page - Renesas Technology Corp

No. de pieza H8SX1663
Descripción Electrónicos  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
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H8SX1663 Datasheet(HTML) 783 Page - Renesas Technology Corp

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Section 15 Serial Communication Interface (SCI, IrDA, CRC)
Rev.1.00 Jun. 07, 2006 Page 731 of 1102
REJ09B0294-0100
Initialization
Read data from RDR and
clear RDRF flag in SSR to 0
Clear RE bit in SCR to 0
Start reception
Start
Error processing
No
No
No
Yes
Yes
ORER = 0
and PER = 0?
RDRF = 1?
All data received?
Yes
Figure 15.33 Sample Reception Flowchart
15.7.8
Clock Output Control
Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set
to 1. Specifically, the minimum width of a clock pulse can be specified.
Figure 15.34 shows an example of clock output fixing timing when the CKE0 bit is controlled
with GM = 1 and CKE1 = 0.
Given pulse width
SCK
CKE0
Given pulse width
Figure 15.34 Clock Output Fixing Timing



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