H8SLASH3021 datasheet(151/712 Pages) RENESAS

No. de pieza	H8/3021

Descripción Electrónicos	16-Bit Single-Chip Microcomputer

PDF	712 Pages

Scroll/Zoom	100%

Fabricante Electrónico	RENESAS [Renesas Technology Corp]

Página de inicio	http://www.renesas.com

Logo

151 / 712 page

6. Bus Controller

Rev.2.00 Mar. 22, 2007 Page 127 of 684

REJ09B0352-0200

6.4

Usage Notes

6.4.1

ASTCR and WCER Write Timing: Data written to ASTCR or WCER takes effect starting from

the next bus cycle. Figure 6.11 shows the timing when an instruction fetched from area 2 changes

area 2 from three-state access to two-state access.

Address

ASTCR address

3-state access to area 2

2-state access

to area 2

Figure 6.11 ASTCR Write Timing

6.4.2

Precautions on setting ASTCR and ABWCR*

Use the H8/3022 Group on-chip program to set ASTCR and ABWCR as shown below, so that the

on-chip ROM access cycle for H8/3022 Group can be emulated using the evaluation chip for

support tools.

Modes 5 and 7

ASTCR0 = 0

ABWCR = H'FC

Note:

The ABWCR (bus width control register; lower 16-bit address: H'FFEC) is not built onto

this LSI. For detailed features of the ABWCR, see the H8/3048 Group, H8/3048 F-ZTAT

Hardware Manual.

H8/3021 Datasheet(PDF) 151 Page - Renesas Technology Corp