H8SLASH3021 datasheet(191/712 Pages) RENESAS

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7. I/O Ports

Rev.2.00 Mar. 22, 2007 Page 167 of 684

REJ09B0352-0200

7.10.2

Table 7.15 summarizes the registers of port A.

Table 7.15

Port A Registers

Initial Value

Address*

Name

Abbreviation

R/W

Modes 1, 5, and 7

Modes 3 and 6

H'FFD1

Port A data direction

PADDR

H'00

H'80

H'FFD3

Port A data register

PADR

R/W

H'00

Note:

Lower 16 bits of the address.

Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select

input or output for each pin in port A. The corresponding PADDR bit should also be set when a

pin is used as a TPC output.

PA DDR

—

Port A data direction 7 to 0

These bits select input or output for port A pins

PA DDR

Bit

Initial value

Read/Write

Initial value

Read/Write

Modes

1, 5, and 7

Modes 3

and 6

A pin in port A becomes an output pin if the corresponding PADDR bit is set to 1, and an input

pin if this bit is cleared to 0. However, in modes 3 and 6, PA

7 DDR is fixed at 1, and PA7

functions as an address output pin.

PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.

PADDR is initialized to H'00 in modes 1, 5 and 7 and to H'80 in modes 3 and 6 by a reset and in

hardware standby mode. In software standby mode it retains its previous setting. If a PADDR bit

is set to 1, the corresponding pin maintains its output state in software standby mode.

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