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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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H8/3021 Datasheet(PDF) 233 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 233 Page - Renesas Technology Corp |
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233 / 712 page  8. 16-Bit Integrated Timer Unit (ITU) Rev.2.00 Mar. 22, 2007 Page 209 of 684 REJ09B0352-0200 Bit 1—Master Enable TIOCA 4 (EA4): Enables or disables ITU output at pin TIOCA4. Bit 1 EA4 Description 0 TIOCA 4 output is disabled regardless of TIOR4, TMDR, and TFCR settings (TIOCA4 operates as a generic input/output pin). If XTGD = 0, EA4 is cleared to 0 when input capture A occurs in channel 1. 1 TIOCA 4 is enabled for output according to TIOR4, TMDR, and TFCR settings (Initial value) Bit 0—Master Enable TIOCA 3 (EA3): Enables or disables ITU output at pin TIOCA3. Bit 0 EA3 Description 0 TIOCA 3 output is disabled regardless of TIOR3, TMDR, and TFCR settings (TIOCA3 operates as a generic input/output pin). If XTGD = 0, EA3 is cleared to 0 when input capture A occurs in channel 1. 1 TIOCA 3 is enabled for output according to TIOR3, TMDR, and TFCR settings (Initial value) |
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