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H8/3021 Datasheet(PDF) 260 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 260 Page - Renesas Technology Corp |
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260 / 712 page ![]() 8. 16-Bit Integrated Timer Unit (ITU) Rev.2.00 Mar. 22, 2007 Page 236 of 684 REJ09B0352-0200 • Input capture signal timing Input capture on the rising edge, falling edge, or both edges can be selected by settings in TIOR. Figure 8.25 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges. N N φ Input-capture input Internal input capture signal TCNT GRA, GRB Figure 8.25 Input Capture Signal Timing |
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