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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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H8/3021 Datasheet(PDF) 279 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 279 Page - Renesas Technology Corp |
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279 / 712 page  8. 16-Bit Integrated Timer Unit (ITU) Rev.2.00 Mar. 22, 2007 Page 255 of 684 REJ09B0352-0200 ⎯ General register settings outside the counting range (H'0000 to GRA3) Waveforms with a duty cycle of 0 % or 100% can be output by setting a general register to a value outside the counting range. When a buffer register is set to a value outside the counting range, then later restored to a value within the counting range, the counting direction (up or down) must be the same both times. See figure 8.42. 0 % duty cycle 100 % duty cycle Write during down-counting Write during up-counting GRA3 GR H'0000 Output pin Output pin BR GR Figure 8.42 Changing a General Register Setting by Buffer Transfer (Example 2) Settings can be made in this way by detecting GRA3 compare match or TCNT4 underflow before writing to the buffer register. |
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