H8SLASH3021 datasheet(317/712 Pages) RENESAS

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9. Programmable Timing Pattern Controller

Rev.2.00 Mar. 22, 2007 Page 293 of 684

REJ09B0352-0200

9.2.5

Next Data Register A (NDRA)

NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups

1 and 0 (pins TP

7 to TP0). During TPC output, when an ITU compare match event specified in

TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The address of

NDRA differs depending on whether TPC output groups 0 and 1 have the same output trigger or

different output triggers.

NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Same Trigger for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by

the same compare match event, the NDRA address is H'FFA5. The upper 4 bits belong to group 1

and the lower 4 bits to group 0. Address H'FFA7 consists entirely of reserved bits that cannot be

modified and always read 1.

Address H'FFA5

Bit

Initial value

Read/Write

NDR7

R/W

NDR6

R/W

NDR5

R/W

NDR4

R/W

NDR3

R/W

NDR2

R/W

NDR1

R/W

NDR0

R/W

Next data 7 to 4

These bits store the next output

data for TPC output group 1

Next data 3 to 0

These bits store the next output

data for TPC output group 0

Address H'FFA7

Bit

Initial value

Read/Write

—

Reserved bits

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