H8SLASH3003 datasheet(234/715 Pages) RENESAS

No. de pieza	H8/3003

Descripción Electrónicos	microcontroller (MCU)

PDF	715 Pages

Scroll/Zoom	100%

Fabricante Electrónico	RENESAS [Renesas Technology Corp]

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8.4.8 DMAC Bus Cycle

Figure 8-13 shows an example of the timing of the basic DMAC bus cycle. This example shows a

word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When the

DMAC gets the bus from the CPU, after one dead cycle (Td), it reads from the source address and

writes to the destination address. During these read and write operations the bus is not released

even if there is another bus request. DMAC cycles comply with bus controller settings in the same

way as CPU cycles.

Figure 8-13 DMA Transfer Bus Timing (Example)

Figure 8-14 shows the timing when the DMAC is activated by low input at a

DREQ pin. This

example shows a word-size transfer from a 16-bit two-state access area to another 16-bit two-state

access area. The DMAC continues the transfer while the

DREQ pin is held low.

to A

HWR

LWR

CPU cycle

DMAC cycle (word transfer)

CPU cycle

Source

address

Destination address

216

H8/3003 Datasheet(PDF) 234 Page - Renesas Technology Corp