H8SLASH3003 datasheet(248/715 Pages) RENESAS

248 / 715 page

8.5 Interrupts

The DMAC generates only DMA-end interrupts. Table 8-13 lists the interrupts and their priority.

Table 8-13 DMAC Interrupts

Description

Group

Interrupt

Short Address Mode

Full Address Mode

Interrupt Priority

DEND0A

End of transfer on channel 0A

End of transfer on

High

channel 0

DEND0B

End of transfer on channel 0B

—

DEND1A

End of transfer on channel 1A

End of transfer on

channel 1

DEND1B

End of transfer on channel 1B

—

DEND2A

End of transfer on channel 2A

End of transfer on

channel 2

DEND2B

End of transfer on channel 2B

—

DEND3A

End of transfer on channel 3A

End of transfer on

channel 3

DEND3B

End of transfer on channel 3B

—

Low

Each interrupt is enabled or disabled by the DTIE bit in the corresponding data transfer control

The interrupt priority order among channels is channel 0 > channel 1 > channel 2 > channel 3, and

channel A > channel B. The interrupt priority order between groups can be modified in interrupt

priority register B (IPRB).

Figure 8-26 shows the DMA-end interrupt logic. An interrupt is requested whenever DTE = 0 and

DTIE = 1.

230

H8/3003 Datasheet(PDF) 248 Page - Renesas Technology Corp

H8/3003 Datasheet(HTML) 248 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL