H8SLASH3003 datasheet(253/715 Pages) RENESAS

No. de pieza	H8/3003

Descripción Electrónicos	microcontroller (MCU)

PDF	715 Pages

Scroll/Zoom	100%

Fabricante Electrónico	RENESAS [Renesas Technology Corp]

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Table 8-14 Address Ranges Specifiable in MAR and IOAR

1-Mbyte Mode

16-Mbyte Mode

MAR

H'00000 to H'FFFFF

H'000000 to H'FFFFFF

(0 to 1048575)

(0 to 16777215)

IOAR

H'FFF00 to H'FFFFF

H'FFFF00 to H'FFFFFF

(1048320 to 1048575)

(16776960 to 16777215)

MAR bits 23 to 20 are ignored in 1-Mbyte mode.

8.6.8 Bus Cycle when Transfer is Aborted

When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the DTME

bit, if this halts a channel for which the DMAC has a transfer request pending internally, a dead

cycle occurs. This dead cycle does not update the halted channel’s address register or counter

value. Figure 8-28 shows an example in which an auto-requested transfer in cycle-steal mode on

channel 0 is aborted by clearing the DTE bit in channel 0.

Figure 8-28 Bus Timing at Abort of DMA Transfer in Cycle-Steal Mode

Address bus

GW, LWR

CPU cycle

DMAC cycle

CPU cycle

DMAC

cycle

CPU cycle

DTE bit is

cleared

235

H8/3003 Datasheet(PDF) 253 Page - Renesas Technology Corp