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H8/3028F Datasheet(PDF) 355 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 355 Page - Renesas Technology Corp |
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355 / 923 page ![]() Rev. 2.00, 09/03, page 325 of 890 Bit 5—Input Capture/Compare Match Interrupt Enable B1 (IMIEB1): Enables or disables the interrupt requested by the IMFB1 when IMFB1 flag is set to 1. Bit 5 IMIEB1 Description 0 IMIB1 interrupt requested by IMFB1 flag is disabled (Initial value) 1 IMIB1 interrupt requested by IMFB1 flag is enabled Bit 4—Input Capture/Compare Match Interrupt Enable B0 (IMIEB0): Enables or disables the interrupt requested by the IMFB0 when IMFB0 flag is set to 1. Bit 4 IMIEB0 Description 0 IMIB0 interrupt requested by IMFB0 flag is disabled (Initial value) 1 IMIB0 interrupt requested by IMFB0 flag is enabled Bit 3—Reserved: This bit cannot be modified and is always read as 1. Bit 2—Input Capture/Compare Match Flag B2 (IMFB2): This status flag indicates GRB2 compare match or input capture events. Bit 2 IMFB2 Description 0 [Clearing condition] (Initial value) Read IMFB2 flag when IMFB2 =1, then write 0 in IMFB2 flag 1 [Setting conditions] • 16TCNT2 = GRB2 when GRB2 functions as an output compare register • 16TCNT2 value is transferred to GRB2 by an input capture signal when GRB2 functions as an input capture register |
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