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H8/3028F Datasheet(PDF) 107 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 107 Page - Renesas Technology Corp |
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107 / 923 page ![]() Rev. 2.00, 09/03, page 77 of 890 4.4 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1 in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, which is specified in the instruction code. |
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