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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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H8/3028F Datasheet(PDF) 185 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 185 Page - Renesas Technology Corp |
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185 / 923 page  Rev. 2.00, 09/03, page 155 of 890 φ A23 to A0 CSn (RAS) AS Tp1 Tr Tc1 ( UCAS/LCAS) PB4/PB5 RD (WE) D15 to D0 RD (WE) D15 to D0 ( UCAS/LCAS) PB4/PB5 Tc2 Tp2 Note: n = 2 to 5 Row High level High level Column Read access Write access Figure 6.19 Timing with Two Precharge States (CSEL = 0 in DRCRB) 6.5.8 Wait Control In a DRAM access cycle, wait states can be inserted (1) between the Tr state and Tc1 state, and (2) between the Tc1 state and Tc2 state. Insertion of Trw Wait State between Tr and Tc1: One Trw state can be inserted between Tr and Tc1 by setting the RCW bit to 1 in DRCRB. Insertion of Tw Wait State(s) between Tc1 and Tc2: When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from 0 to 3 wait states can be inserted between the Tc1 state and Tc2 state by means of settings in WCRH and WCRL. Figure 6.20 shows an example of the timing for wait state insertion. |
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