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H8/3028F Datasheet(PDF) 230 Page - Renesas Technology Corp

No. de pieza H8/3028F
Descripción Electrónicos  Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
PDF  923 Pages
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
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H8/3028F Datasheet(HTML) 230 Page - Renesas Technology Corp

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Rev. 2.00, 09/03, page 200 of 890
7.3
Register Descriptions (2) (Full Address Mode)
In full address mode the A and B channels operate together. Full address mode is selected as
indicated in table 7.4.
7.3.1
Memory Address Registers (MAR)
A memory address register (MAR) is a 32-bit readable/writable register. MARA functions as the
source address register of the transfer, and MARB as the destination address register.
An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits
of MARR are reserved; they cannot be modified and are always read as 1. (Write is invalid.)
Bit
Initial value
Read/Write
31
—
Source or destination address
30
—
29
—
28
—
27
—
26
—
25
—
24
—
23
R/W
22
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
R/W
15
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
MARR
MARE
MARH
MARL
Undetermined
The MAR value is incremented or decremented each time one byte or word is transferred,
automatically updating the source or destination memory address. For details, see section 7.3.4,
Data Transfer Control Registers (DTCR).
The MARs are not initialized by a reset or in standby mode.
7.3.2
I/O Address Registers (IOAR)
The I/O address registers (IOARs) are not used in full address mode.



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