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H8/3028F Datasheet(PDF) 260 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 260 Page - Renesas Technology Corp |
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260 / 923 page ![]() Rev. 2.00, 09/03, page 230 of 890 Figure 7.14 shows the timing when the DMAC is activated by low input at a DREQ pin. This example shows a word-size transfer from a 16-bit two-state access area to another 16-bit two-state access area. The DMAC continues the transfer while the DREQ pin is held low. φ DREQ RD HWR TEND T1 T2 T3 Td T1 T2 T1 T2 T1 T2 Td T1 T2 T1 T2 T1 T2 LWR , CPU cycle DMAC cycle CPU cycle DMAC cycle (last transfer cycle) CPU cycle Source address Destination address Source address Destination address Address bus Figure 7.14 Bus Timing of DMA Transfer Requested by Low DREQ DREQ DREQ DREQ Input |
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