H8SLASH3028F datasheet(297/923 Pages) RENESAS

297 / 923 page

Rev. 2.00, 09/03, page 267 of 890

8.7

Port 6

8.7.1

Overview

Port 6 is an 8-bit input/output port that is also used for input and output of bus control signals

(

LWR, HWR, RD, AS, BACK, BREQ, WAIT) and for clock (φ) output.

In modes 1 to 5 (expanded modes), the pin functions are P67 (generic input)/φ, LWR, HWR, RD,

AS, P6

2/BACK, P61/BREQ, and P60/WAIT). See table 8.11 for the selection of the pin functions.

In modes 6 and 7 (single-chip modes), P67 functions as a generic input port or φ output, and P66 to

P60 function as generic input/output ports.

When DRAM is connected to areas 2 to 5,

LWR, HWR, and RD also function as LCAS, UCAS,

and

WE, respectively. For details see section 6.5, DRAM Interface.

Pins in port 6 can drive one TTL load and a 90-pF capacitive load. They can also drive a

darlington transistor pair.

Port 6

P6 /

LWR

HWR

BACK

BREQ

WAIT

Port 6 pins

LWR

HWR

BACK

BREQ

WAIT

Modes 1 to 5

(expanded modes)

(output)

(input)

Mode 6 and 7

(single-chip mode)

(input) / φ(output)

(input/output)

P67 (input)/

P62 (input/output)/

P61 (input/output)/

P60 (input/output)/

Figure 8.6 Port 6 Pin Configuration

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