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CY23S08
Document #: 38-07265 Rev. *H
Page 2 of 10
Pinouts
Figure 1. 16-Pin SOIC Package
Table 1. Pin Definition - 16-Pin SOIC Package
Pin
Signal
Description
1REF[2]
Input reference frequency, 5V tolerant input
2
CLKA1[3]
Clock output, Bank A
3
CLKA2[3]
Clock output, Bank A
4VDD
3.3V supply
5
GND
Ground
6
CLKB1[3]
Clock output, Bank B
7
CLKB2[3]
Clock output, Bank B
8S2[4]
Select input, bit 2
9S1[4]
Select input, bit 1
10
CLKB3[3]
Clock output, Bank B
11
CLKB4[3]
Clock output, Bank B
12
GND
Ground
13
VDD
3.3V supply
14
CLKA3[3]
Clock output, Bank A
15
CLKA4[3]
Clock output, Bank A
16
FBK
PLL feedback input
9
16
FBK
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
1
2
3
4
5
6
7
8
10
11
12
13
14
15
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
Top View
SOIC
Notes
1. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY23S08–2.
2. Weak pull down.
3. Weak pull down on all outputs.
4. Weak pull ups on these inputs.
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