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ATmega324P Datasheet(PDF) 130 Page - ATMEL Corporation |
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ATmega324P Datasheet(HTML) 130 Page - ATMEL Corporation |
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130 / 377 page  130 7674F–AVR–09/09 ATmega164P/324P/644P Figure 14-10. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling Figure 14-11 shows the same timing data, but with the prescaler enabled. Figure 14-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f clk_I/O/8) Figure 14-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn Flag at BOTTOM. clk Tn (clk I/O/1) OCFnx clk I/O OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCFnx OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 clk I/O clk Tn (clk I/O/8) |
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