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ATtiny48 Datasheet(PDF) 212 Page - ATMEL Corporation

No. de pieza ATtiny48
Descripción Electrónicos  8-bit Microcontroller with 4/8K Bytes In-System Programmable Flash
PDF  266 Pages
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Fabricante Electrónico  ATMEL [ATMEL Corporation]
Página de inicio  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATtiny48 Datasheet(HTML) 212 Page - ATMEL Corporation

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212
8008C–AVR–03/09
ATtiny48/88
Figure 21-8. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements
(1)
Note:
1. The timing requirements shown in Figure 21-6 (i.e., tDVXH, tXHXL, and tXLDX) also apply to read-
ing operation.
CLKI
OE
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
DATA
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
t
BVDV
t
OLDV
t
XLOL
t
OHDZ
Table 21-9.
Parallel Programming Characteristics, T
A = 25°C, VCC = 5V
Symbol
Parameter
Min
Typ
Max
Units
VPP
Programming Enable Voltage
11.5
12.5
V
IPP
Programming Enable Current
250
μA
tDVXH
Data and Control Valid before CLKI High
67
ns
tXLXH
CLKI Low to CLKI High
200
ns
tXHXL
CLKI Pulse Width High
150
ns
tXLDX
Data and Control Hold after CLKI Low
67
ns
tXLWL
CLKI Low to WR Low
0
ns
tXLPH
CLKI Low to PAGEL high
0
ns
tPLXH
PAGEL low to CLKI high
150
ns
tBVPH
BS1 Valid before PAGEL High
67
ns
tPHPL
PAGEL Pulse Width High
150
ns
tPLBX
BS1 Hold after PAGEL Low
67
ns
tWLBX
BS2/1 Hold after WR Low
67
ns
tPLWL
PAGEL Low to WR Low
67
ns
tBVWL
BS1 Valid to WR Low
67
ns
tWLWH
WR Pulse Width Low
150
ns
tWLRL
WR Low to RDY/BSY Low
0
1
μs
tWLRH
WR Low to RDY/BSY High
(1)
3.7
4.5
ms



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