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H5GQ1H24AFR-R0C Datasheet(PDF) 105 Page - Hynix Semiconductor

No. de pieza H5GQ1H24AFR-R0C
Descripción Electrónicos  1Gb (32Mx32) GDDR5 SGRAM
PDF  173 Pages
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Fabricante Electrónico  HYNIX [Hynix Semiconductor]
Página de inicio  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5GQ1H24AFR-R0C Datasheet(HTML) 105 Page - Hynix Semiconductor

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009
105
H5GQ1H24AFR
Figure 70. REFRESH command
Figure 71. Refresh Timings
CS#
WE#
CAS#
RAS#
CKE#
A9‐A11 (A12)
A0,A1,A6
A8
BA0‐BA3
A2‐A5
LOW
Refresh
CK
CK#
A7
CK#
CK
CMD
tKO
DQ
NOP
PRE 
ALL
BA = bank address; RA = row address
WRTR and RDTR commands are allowed during refresh unless disabled in the Mode Register
REF
ADDR
T0
T1
Ta0
Ta1
Tb0
Tb1
Tb2
Tb3
Tb4
Tb5
Tc0
NOP
WRTR
NOP
NOP
NOP
NOP
NOP
ACT
WCK
WCK#
WL = 3
tRP
tRFC
tREFTR
Donʹt Care
BA
RA
WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines 
the needed offset between WCK and CK.



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