MPC8308 datasheet(5/2 Pages) FREESCALE

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MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2

Freescale Semiconductor

Electrical Characteristics

Figure 2 shows the undershoot and overshoot voltages at the interfaces of the device.

Figure 2. Overshoot/Undershoot Voltage for GVDD/NVDD/LVDD

2.1.3

Output Driver Characteristics

Table 3 provides information on the characteristics of the output driver strengths.

2.1.4

Power Sequencing

The device does not require the core supply voltage (VDD) and IO supply voltages (GVDD, LVDD, and

NVDD) to be applied in any particular order. Note that during power ramp-up, before the power supplies

are stable and if the I/O voltages are supplied before the core voltage, there might be a period of time that

all input and output pins are actively driven and cause contention and excessive current. In order to avoid

actively driving the I/O pins and to eliminate excessive current draw, apply the core voltage (VDD) before

the I/O voltage (GVDD, LVDD, and NVDD) and assert PORESET before the power supplies fully ramp up.

In the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal

value before the I/O supplies reach 0.7 V; see Figure 3.

Table 3. Output Drive Capability

Driver Type

Output Impedance (

Ω)

Supply Voltage

Local bus interface utilities signals

NVDD = 3.3 V

DDR2 signals1

1 Output Impedance can also be adjusted through configurable options in DDR Control Driver Register (DDRCDR).

For more information, see the

MPC8308 PowerQUICC II Pro Processor Reference Manual.

GVDD = 1.8 V

DUART, system control, I2C, JTAG, eSDHC, GPIO,SPI, USB

NVDD = 3.3 V

eTSEC signals

LVDD = 2.5/3.3 V

VSS

VSS – 0.3 V

VSS – 0.7 V

Not to Exceed 10%

G/L/NVDD + 20%

G/L/NVDD

G/L/NVDD + 5%

of tinterface

1. Note that tinterface refers to the clock period associated with the bus clock interface.

VIH

VIL

Note:

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