PIC16F720-ESLASHML datasheet(115/244 Pages) MICROCHIP

115 / 244 page

 2010 Microchip Technology Inc.

DS41430A-page 115

PIC16F/LF720/721

15.3.2

PWM PERIOD

The PWM period is specified by the PR2 register of

Timer2. The PWM period can be calculated using the

formula of Equation 15-1.

EQUATION 15-1:

PWM PERIOD

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

• TMR2 is cleared

• The CCP1 pin is set. (Exception: If the PWM duty

cycle = 0%, the pin will not be set.)

• The PWM duty cycle is latched from CCPR1L into

CCPR1H.

15.3.3

PWM DUTY CYCLE

The PWM duty cycle is specified by writing a 10-bit value

to multiple registers: CCPR1L register and DC1 and B1

bits of the CCP1CON register. The CCPR1L contains

the eight MSbs and the DC1 and B1 bits of the

CCP1CON register contain the two LSbs. CCPR1L and

DC1 and B1 bits of the CCP1CON register can be

written to at any time. The duty cycle value is not latched

into CCPR1H until after the period completes (i.e., a

match between PR2 and TMR2 registers occurs). While

using the PWM, the CCPR1H register is read-only.

Equation 15-2 is used to calculate the PWM pulse

width.

Equation 15-3 is used to calculate the PWM duty cycle

ratio.

EQUATION 15-2:

PULSE WIDTH

EQUATION 15-3:

DUTY CYCLE RATIO

The CCPR1H register and a 2-bit internal latch are

used to double buffer the PWM duty cycle. This double

buffering is essential for glitchless PWM operation.

The 8-bit timer TMR2 register is concatenated with

either the 2-bit internal system clock (FOSC), or 2 bits of

the prescaler, to create the 10-bit time base. The system

clock is used if the Timer2 prescaler is set to 1:1.

When the 10-bit time base matches the CCPR1H and

2-bit latch, then the CCP1 pin is cleared (refer to

Figure 15-3).

Note:

The

Timer2

postscaler

(refer

Section 14.1 “Timer2 Operation”) is not

used in the determination of the PWM

frequency.

PWM Period

PR2

 1

 4TOSC 



(TMR2 Prescale Value)

Note:

TOSC = 1/FOSC

Pulse Width

CCPR1L:CCP1CON<5:4>





TOSC

 (TMR2 Prescale Value)

Note: TOSC = 1/FOSC

Duty Cycle Ratio

CCPR1L:CCP1CON<5:4>



4PR2



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