PIC16F720-ESLASHML datasheet(125/244 Pages) MICROCHIP

125 / 244 page

 2010 Microchip Technology Inc.

DS41430A-page 125

PIC16F/LF720/721

16.1.2.7

Address Detection

A special Address Detection mode is available for use

when multiple receivers share the same transmission

line, such as in RS-485 systems. Address detection is

enabled by setting the ADDEN bit of the RCSTA

Address detection requires 9-bit character reception.

When address detection is enabled, only characters

with the ninth data bit set will be transferred to the

receive FIFO buffer, thereby setting the RCIF interrupt

bit of the PIR1 register. All other characters will be

ignored.

Upon receiving an address character, user software

determines if the address matches its own. Upon

address match, user software must disable address

detection by clearing the ADDEN bit before the next

Stop bit occurs. When user software detects the end of

the message, determined by the message protocol

used, software places the receiver back into the

Address Detection mode by setting the ADDEN bit.

16.1.2.8

Asynchronous Reception Setup:

Initialize the SPBRG register and the BRGH bit

to achieve the desired baud rate (refer to

Section 16.2 “AUSART Baud Rate Generator

(BRG)”).

Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

If 9-bit reception is desired, set the RX9 bit.

Enable reception by setting the CREN bit.

The RCIF interrupt flag bit of the PIR1 register

will be set when a character is transferred from

the RSR to the receive buffer. An interrupt will be

generated if the RCIE bit of the PIE1 register

was also set.

Read the RCSTA register to get the error flags

and, if 9-bit data reception is enabled, the ninth

data bit.

Get the received 8 Least Significant data bits

from the receive buffer by reading the RCREG

If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

16.1.2.9

9-bit Address Detection Mode Setup

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

Initialize the SPBRG register and the BRGH bit

to achieve the desired baud rate (refer to

Section 16.2 “AUSART Baud Rate Generator

(BRG)”).

Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

Enable 9-bit reception by setting the RX9 bit.

Enable address detection by setting the ADDEN

bit.

Enable reception by setting the CREN bit.

The RCIF interrupt flag bit of the PIR1 register

will be set when a character with the ninth bit set

is transferred from the RSR to the receive buffer.

An interrupt will be generated if the RCIE inter-

rupt enable bit of the PIE1 register was also set.

Read the RCSTA register to get the error flags.

The ninth data bit will always be set.

Get the received 8 Least Significant data bits

from the receive buffer by reading the RCREG

device’s address.

10. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

11. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and generate interrupts.

PIC16F720-E/ML Datasheet(PDF) 125 Page - Microchip Technology

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