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STM32F407IG Datasheet(PDF) 131 Page - STMicroelectronics |
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STM32F407IG Datasheet(HTML) 131 Page - STMicroelectronics |
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131 / 167 page ![]() STM32F405xx, STM32F407xx Electrical characteristics Doc ID 022152 Rev 2 131/167 Synchronous waveforms and timings Figure 56 through Figure 59 represent synchronous waveforms and Table 76 through Table 78 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: ● BurstAccessMode = FSMC_BurstAccessMode_Enable; ● MemoryType = FSMC_MemoryType_CRAM; ● WriteBurst = FSMC_WriteBurst_Enable; ● CLKDivision = 1; (0 is not supported, see the STM32F40xxx/41xxx reference manual) ● DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM In all timing tables, the THCLK is the HCLK clock period (with maximum FSMC_CLK = 60 MHz). Figure 56. Synchronous multiplexed NOR/PSRAM read timings |
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