OMAP3530ECBC72 datasheet(151/264 Pages) TI1

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5.3 Analog Supply (vdda_dac) Noise Requirements

supply variation as shown in the following equation:

OUTFS

OUT

DAC

PSRR

100

%FSR

100kHz 1MHz

PSRR(%FSR/V)

Firstpoleof

DACoutputload

030-019

OMAP3530/25 Applications Processor

www.ti.com

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

In order to assure 10-bit accuracy of the DAC analog output, the analog supply vdda_dac has to meet the

noise requirements stated in this section.

The DAC Power Supply Rejection Ratio is defined as the relative variation of the full-scale output current

divided by the supply variation. Thus, it is expressed in percentage of Full-Scale Range (FSR) per volt of

Depending on frequency, the PSRR is defined in Table 5-4.

Table 5-4. Video DAC – Power Supply Rejection Ratio

Supply Noise Frequency

PSRR % FSR/V

0 to 100 kHz

> 100 kHz

The rejection decreases 20 dB/dec.

Example: at 1 MHz the PSRR is 10% of FSR/V

A graphic representation is shown in Figure 5-2.

Figure 5-2. Video DAC – Power Supply Rejection Ratio

To ensure that the DAC SFDR specification is met, the PSRR values and the clock jitter requirements

translate to the following limits on vdda_dac (for the Video DAC).

The maximum peak-to-peak noise on vdda (ripple) is defined in Table 5-5:

Table 5-5. Video DAC – Maximum Peak-to-Peak Noise on vdda_dac

Tone Frequency

Maximum Peak-to-Peak Noise on vdda_dac

0 to 100 kHz

< 30 mVpp

> 100 kHz

Decreases 20 dB/dec.

Example: at 1 MHz the maximum is 3 mVpp

The maximum noise spectral density (white noise) is defined in Table 5-6:

Table 5-6. Video DAC – Maximum Noise Spectral Density

Supply Noise Bandwidth

Maximum Supply Noise Density

0 to 100 kHz

< 20

µV / √Hz

> 100 kHz

Decreases 20 dB/dec.

Example: at 1 MHz the maximum noise density is 2

µ / √Hz

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VIDEO DAC SPECIFICATIONS

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