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STM32F205RB Datasheet(PDF) 135 Page - STMicroelectronics

No. de pieza STM32F205RB
Descripción Electrónicos  ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/1284KB RAM
PDF  178 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F205RB Datasheet(HTML) 135 Page - STMicroelectronics

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DocID15818 Rev 11
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STM32F20xxx
Electrical characteristics
177
Synchronous waveforms and timings
Figure 60 through Figure 63 represent synchronous waveforms and Table 77 through
Table 79 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
•
BurstAccessMode = FSMC_BurstAccessMode_Enable;
•
MemoryType = FSMC_MemoryType_CRAM;
•
WriteBurst = FSMC_WriteBurst_Enable;
•
CLKDivision = 1; (0 is not supported, see the STM32F20xxx/21xxx reference manual)
•
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
In all timing tables, the THCLK is the HCLK clock period.
Figure 60. Synchronous multiplexed NOR/PSRAM read timings
FSMC_CLK
FSMC_NEx
FSMC_NADV
FSMC_A[25:16]
FSMC_NOE
FSMC_AD[15:0]
AD[15:0]
D1
D2
FSMC_NWAIT
(WAITCFG = 1b, WAITPOL + 0b)
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
tw(CLK)
tw(CLK)
Data latency = 0
BUSTURN = 0
td(CLKL-NExL)
td(CLKL-NExH)
td(CLKL-NADVL)
td(CLKL-AV)
td(CLKL-NADVH)
td(CLKL-AIV)
td(CLKH-NOEL)
td(CLKL-NOEH)
td(CLKL-ADV)
td(CLKL-ADIV)
tsu(ADV-CLKH)
th(CLKH-ADV)
tsu(ADV-CLKH)
th(CLKH-ADV)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
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