STM32F217VG datasheet(120/173 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F21xxx

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Doc ID 17050 Rev 8

INL(3)

Integral non linearity

(difference between

measured value at Code i

and the value at Code i on a

line drawn between Code 0

and last Code 1023)

±1

LSB

Given for the DAC in 10-bit

configuration.

±4

LSB

Given for the DAC in 12-bit

configuration.

Offset(3)

Offset error

(difference between

measured value at Code

(0x800) and the ideal value =

VREF+/2)

±10

Given for the DAC in 12-bit

configuration

±3

LSB

Given for the DAC in 10-bit at

VREF+ = 3.6 V

±12

LSB

Given for the DAC in 12-bit at

VREF+ = 3.6 V

Gain

error(3)

Gain error

±0.5

Given for the DAC in 12-bit

configuration

tSETTLING

(3)

Settling time (full scale: for a

10-bit input code transition

between the lowest and the

highest input codes when

DAC_OUT reaches final

value ±4LSB

-3

µs

CLOAD ≤ 50 pF,

RLOAD ≥ 5 kΩ

THD(3)

Total Harmonic Distortion

Buffer ON

CLOAD ≤ 50 pF,

RLOAD ≥ 5 kΩ

Update

rate(1)

Max frequency for a correct

DAC_OUT change when

small variation in the input

code (from code i to i+1LSB)

MS/s

CLOAD ≤ 50 pF,

RLOAD ≥ 5 kΩ

tWAKEUP

(3)

Wakeup time from off state

(Setting the ENx bit in the

DAC Control register)

-6.5

µs

CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

input code between lowest and

highest possible ones.

PSRR+ (1)

Power supply rejection ratio

(to VDDA) (static DC

measurement)

–67

–40

No RLOAD, CLOAD = 50 pF

Guaranteed by design, not tested in production.

The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic

consumption occurs.

Guaranteed by characterization, not tested in production.

Table 65.

DAC characteristics (continued)

Symbol

Parameter

Min

Typ

Max

Unit

Comments

STM32F217VG Datasheet(PDF) 120 Page - STMicroelectronics

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