LAN9500AI datasheet(151/213 Pages) MICROCHIP

No. de pieza	LAN9500AI

Descripción Electrónicos	LAN950x USB 2.0 to 10/100 Ethernet Controller

PDF	213 Pages

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Fabricante Electrónico	MICROCHIP [Microchip Technology]

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 2010 - 2015 Microchip Technology Inc.

DS00001875A-page 151

LAN950x

7.3.25

TRANSMIT FIFO LEVEL DEBUG REGISTER (DBG_TX_FIFO_LVL)

Address:

078h

Size:

32 bits

Bits

Description

Type

Default

31:28

RESERVED

27:16

TX FIFO Read Level (TXRDLVL)

This is a DWORD count defined as follows:

The count is increased by the number of DWORDs contained in the packet

after the ENTIRE packet has been written into the FIFO.

As a packet is read from the FIFO, it is decremented each time a DWORD

is read.

Note:

Rewinds not supported.

000h

15:12

RESERVED

11:0

TX FIFO Write Level (TXWRLVL)

This is a DWORD count defined as follows:

As a packet is written into the FIFO, it is incremented each time a DWORD

is written.

Whenever a COMPLETE packet has been read from the FIFO, it is

decreased by the number of DWORDs contained in the packet.

On rewind, it is decreased by the number of DWORDs of the packet that has

currently been transferred into the FIFO.

Note:

Write side rewinds are supported, i.e., if a USB packet is received

with an error, the packet is rewound out and re-received from the

host.

000h

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