PC87366 datasheet(124/240 Pages) NSC

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4.0 Fan Speed Control (Continued)

124

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4.3

FAN SPEED CONTROL REGISTERS

The following abbreviations are used to indicate the Register Type:

• R/W = Read/Write

• R = Read from a speciﬁc address returns the value of a speciﬁc register. Write to the same address is to a different

• W=Write

• RO = Read Only

• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

4.3.1

Fan Speed Control Register Map

4.3.2

Fan Speed Control Pre-Scale Register (FCPSR)

Location:

Device specific

Type:

R/W

Offset

Mnemonic

Type

Section

Device speciﬁcNote 1.

Note 1. The location of this register is defined in the

Device Architecture and Conﬁguration chapter.

FCPSR

Fan Speed Control Pre-Scale

R/W

4.3.2

Device speciﬁcNote 1.

FCDCR

Fan Speed Control Duty Cycle

R/W

4.3.3

Bit

76543210

Name

Clock

Select

Pre-Scale Value

Reset

00000000

Bit

Description

Clock Select. This bit selects the input clock for the clock divider.

0: 24 MHz

1: 200 KHz

6-0

Pre-Scale Value. The clock divider for the input clock (24 MHz or 200 KHz) is Pre-Scale Value + 1. Writing

0000000b to these bits transfers the input clock directly to the counter. The maximum clock divider is 124 (7Bh

+1). These bits must not be programmed with the values 7Ch, 7Dh, 7Eh and 7Fh as this may produce

unpredictable results.

The contents of this register should not be changed when the corresponding Fan Speed Control Enable bit of

the Fan Speed Control Conﬁguration register is 1 (see

Device Architecture and Conﬁguration chapter) as this

may produce unpredictable results.

PC87366 Datasheet(PDF) 124 Page - National Semiconductor (TI)

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